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RT9641A/B
Triple Linear Regulator Controller Support ACPI Control Interface
General Description
The RT9641A/B, paired with either the RT9230 or RT9231 simplifies the implementation of ACPIcompliant designs in microprocessor and computer applications. The IC integrates two linear controllers and a low-current pass transistor, as well as the monitoring and control functions into a 16-pin SOIC package. 5VSB One linear during controller sleep generates the 3.3VDUAL voltage plane from an ATX power supply's output states (S3,S4/S5), powering the PCI slots through an external pass transistor, as instructed by the status of the 3.3VDUAL enable pin. An additional pass transistor is used to switch in the ATX 3.3V output for PCI operation during S0 and S1 (active) operating states. The second linear controller supplies the computer system's 2.5V/3.3V memory power through an external pass transistor in active states. During S3 state, an integrated pass transistor supplies the 2.5V/3.3V sleep-state power. A third controller powers up a 5VDUAL plane by switching in the ATX 5V output in active states, or the ATX 5VSB in sleep states. The RT9641A/B's operating mode (active-state outputs or sleep-state outputs) is selectable through two control pins: S3 and S5. Further control of the logic governing activation of different power modes is offered through two enabling pins: EN3VDL and EN5VDL. In active states, the 3.3VDUAL linear regulator uses an external N-channel pass MOSFET to connect the output (VOUT1) directly to the 3.3V input supplied by an ATX (or equivalent) power supply, while incurring minimal losses. In sleep state, the 3.3VDUAL output is supplied from the ATX 5VSB through a NPN transistor, also external to the controller. Active state power delivery for the 2.5V/3.3V or 2.6V/3.43V VMEM output is done through an external NPN or a NMOS transistor. In sleep states, conduction on this output is transferred to an internal pass transistor. The 5VDUAL output is
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powered through two external MOS transistors. In sleep states, a PMOS (or PNP) transistor conducts the current from the ATX 5VSB output, while in active states, current flow is transferred to a NMOS transistor connected to the ATX 5V output. Similar to the 3.3VDUAL output, the operation of the 5VDUAL output is dictated not only by the status of the S3 and S5 pins, but that of the EN5VDL pin as well.
Features
Provides 3 ACPI-Controlled Voltages - 5V Active/Sleep(5VDUAL) 3.3V Active/Sleep(3.3VDUAL) - 2.5V/3.3V Active/Sleep(VMEM) with RT9641A - 2.6V/3.43V Active and 2.5V/3.3V Sleep(VMEM) with RT9641B Simple Control Design - No Compensation Required Excellent Output Voltage Accuracy - 3.3VDUALOutput 2.0% Sleep States Only - 2.5V/3.3V (2.6V/3.43V) Output 2.0% Both Operational States Fixed Output Voltages Require No Precision External Resistors Small Size - Small External Component Count Selectable 2.5V/3.3V (2.6/3.43) VMEM Output Voltage via FAULT/MSEL Pin - 2.5V/2.6V for RDRAM Memory - 3.3V/3.43V for SDRAM Memory Under-voltage Monitoring of All Outputs with Centralized FAULT Reporting Adjustable Soft-start Function Eliminates 5VSB Perturbations
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RT9641A/B
Ordering Information
RT9641A/B Package type S2 : SOP-16 Operating temperature range C: Commercial standard VMEM voltage A : 2.5V/3.3V B : 2.6V/3.43V RT9641BCS2 (Plastic SOP-16)
Pin Configurations
Part Number RT9641ACS2 (Plastic SOP-16)
5VSB EN3VDL 3V3DLSB 3V3DL EN5VDL S3 S5 GND
Pin Configurations TOP VIEW
1 2 3 4 5 6 7 8 16 15 14 13 12
VSEN2 DRV2 12V SS
5VDL 5VDLSB 10 DLA 9 FAULT/MSEL
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Function Block Diagram
12V 3V3DLSB 3V3DL 5VSB
TO 12V 12V BIAS 12V MONITOR 10.5V/9.5V EA4 _ + 5VSB POR DLA
UV DETECTOR
5VDLSB MONITOR AND CONTROL TEMPERATURE MONITOR (TMON) + _ 1.265V DRV2 _ EA2 TO UV DEECTOR
+
0.2V
+ _
MEM VOLTAGE SELECT COMP
UA COMPARTOR + _ 3.75V _ 5VDL + 5A SS EN3VDL S3
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2
_
40A
+ VSEN2
S5 EN5VDL
GND
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Absolute Maximum Ratings
Supply Voltage (V5VSB) 12V DLA, DRV2 All Other Pins Package Thermal Resistance SOP-16, JA Maximum Junction Temperature Maximum Storage Temperature Range Maximum Lead Temperature (Soldering, 10 sec.) 100C/W 150C -65C to 150C 300C +7.0V GND-0.3V to +14.5V GND-0.3V to V12V+0.3V GND-0.3V to 5VSB+0.3V
Recommended Operating Conditions
Supply Voltage (V5VSB) Secondary Bias Voltage (V12V) Digital Inputs (VS3, VS5, VEN3VDL, VEN5VDL) Junction Temperature Range Ambient Temperature Range CAUTION: Stresses beyond the ratings specified in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. +5V 5% +12V 10% 0 to + 5.5V 0C to 125C 0C to 70C
Electrical Characteristics
(VCC (12VIN) = 12V, GND = 0V, TA = 25C, unless otherwise specified) Parameter VCC Supply Current Operating Supply Current Shutdown Supply Current Rising 5VSB POR Threshold Rising 12V Threshold Soft-start Current Shutdown Soft-start Voltage ISS I5VSB I5VSB(OFF) VSS = 0V, S3 = 0, S5 =0 ------7 2 2.5 10.5 6.5 0.8 20 10 -11 -mA mA V V A Symbol Test Conditions Min Typ Max Units
Power-on Reset, Soft-start, and 12V Monitor
-V To be continued
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Parameter Regulation VSEN2 Nominal Voltage Level VSEN2 Nominal Voltage Level VSEN2 Under-voltage Falling Threshold VSEN2 Under-voltage Hysteresis VSEN2 Output Current DRV2 Output Drive Current DRV2 Output Impedance 3.3V Dual Linear Regulator (VOUT1) Sleep-mode Regulation 3V3DL Nominal Voltage Level 3V3DL Under-voltage Falling Threshold 3V3DL Under-voltage Hysteresis 3V3DLSB Output Drive Current DLA Output Impedance 5V Dual Switch Controller (VOUT3) 5VDL Under-voltage Falling Threshold 5VDL Under-voltage Hysteresis 5VDLSB Output Drive Current Timing Intervals Active to Sleep, Input to Switching Delay Sleep to Active, Input to Switching Delay High Level Threshold Low Level Threshold S3, S5 Internal Pull-up Impedance to 5VSB FAULT Output Impedance Temperature Monitor Fault-level Threshold Shutdown-level Threshold Note:
(1)
Symbol
Test Conditions
Min --
Typ -2.5/2. 3.3/3. 68 7 300 30 200 -3.3 2.24 230 10 90 3.40 350 -10 50
(1)
Max 2.0 -------2.0 -----------0.8 -----
Units % V V % % mA mA % V V mV mA V mV mA S mS V V K C C
2.5V/3.3V (2.6V/3.43V) Linear Regulator (VOUT2) VVSEN VVSEN2 RSEL = 1K RSEL = 1K ----IVSEN2 IDRV2 5VSB = 5V 5VSB = 5V, RSEL = 1K RSEL = 10K 200 20 --V3V3DL ---I3V3DLS 5VSB = 5V 5.0 ---I5VDLSB Td1 Td2 CSS = 0.1F
(1)
5VDLSB = 4V
-40 --2.0 ---
Control I/O (S3, S5, EN3VDL, EN5VDL, FAULT) --50 100 145 155
FAULT = high
---
TDS
--
= 50mS with 0.1F Soft-start capacitor. The delay time is adjustable with td2 = 500xCSS (mS).
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Simplified Power System Diagram
5VIN 12VIN 5VSB 3.3VIN Linear Controller Linear Controller RT9641A/B Control Logic Q5 5VDUAL Q1 VMEM Q4
Q2 Q3
3.3VDUAL FAULT SHUTDOWN S3 S5 EN5VDL EN3VDL
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Functional Pin Description
5VSB (Pin 1) Provide a 5V bias supply for the IC to this pin by connecting it to the ATX 5VSB output. This pin also provides the base bias current for all the external NPN transistors controlled by the IC. The voltage at this pin monitored for power-on reset (POR) purposes. EN3VDL and EN5VDL (Pin 2 and 5) These pins control the logic governing the output behavior in response to S3 and S4/S5 requests. These are digital inputs whose status can only be changed during active states operation or during chip shutdown (SS pin grounded by external open-drain device). The input information is latched-in when entering a sleep state, as well as following 5VSB POR release or exit from shutdown. 3V3DLSB (Pin 3) Connect this pin to the base of a suitable NPN transistor. In sleep states, this transistor is used to regulate the voltage at 3V3DL pin to 3.3V. 3V3DL (Pin 4) Connect this pin to the 3.3V dual output (VOUT1). In sleep states, the voltage at this pin is regulated to 3.3V; in active states, ATX 3.3V output is delivered to this node through a fully on N-MOS transistor. During all operating states, this pin is monitored for undervoltage events. S3 and S5 (Pin 6 and 7) These pins switch the IC's operating state from active (S0, S1) to S3 and S4/S5 sleep states. Connect S3 to SLP_S3 and S5 to SLP_S5. These are digital inputs featuring internal 50k (typical) resistor pull-up to 5VSB. Internal circuitry de-glitches the S3 pin for disturbances. GND (Pin 8) Signal ground for the IC. All voltage levels are measured with respect to this pin. FAULT/MSEL (Pin 9) This is a multiplexed function pin allowing the setting of the memory output voltage to either 2.5V(2.6V) or 3.3V(3.43V) (for RDRAM or SDRAM memory systems). The memory voltage setting is latched-in when SS pin voltage goes up to 0.8V (typically 5mS after POR). In case of an under-voltage on any of the outputs or an over temperature event, this pin is used to report the fault condition by being pulled to 5VSB. DLA (Pin 10) Connect this pin to the gates of suitable N-MOSFETs, which in active states, are used to switch in the ATX 3.3V and 5V outputs into the 3.3VDUAL and 5VDUAL outputs, respectively. 5VDLSB (Pin 11) Connect this pin to the gate of a suitable P-MOSFET or bipolar PNP. In sleep states, this transistor is switched on, connecting the ATX 5VSB output to the 5VDUAL regulator output. When PNP is used, it is recommanded to use a 100 base resistor for base current limiting. 5VDL (Pin 12) Connect this pin to the 5VDUAL output (VOUT3). In either operating state, the voltage at this pin is provided through a fully on MOS transistor. This pin is also monitored for under-voltage events. SS (Pin 13) Connect a small ceramic capacitor (0.1F recommended) from this pin to GND. The internal Soft-start (SS) current source along with the external capacitor creates a voltage ramp used to control the ramp-up of the output voltages. Pulling this pin low with an open-drain device shuts down all the output as well as forces the FAULT pin low. The CSS capacitor is also used to provide a controlled S4/S5 to active transition delay time.
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12V (Pin 14) Connect this pin to the ATX (or equivalent) 12V output. This pin is used to monitor the status of the power supply as well as provide bias for the NMOScompatible output drivers. 12V presence at the chip in the absence of bias voltage, or severe 12V brownout during active states (S0, S1) operation can lead to chip misbehavior. RT9641A/B refuses entering active state before 12V power ready. DRV2 (Pin 15) For the 2.5V RDRAM systems, connect this pin to the base of a suitable NPN transistor. This pass transistor regulates the 2.5V(2.6V) output from the ATX 3.3V during active states operation. For 3.3V SDRAM systems connect this pin to the gate of a suitable N-MOS transistor or the base of a suitable NPN transistor. VSEN2 (Pin 16) Connect this pin to the memory output (VOUT2). In sleep states, this pin is regulated to 2.5V(2.6V) or 3.3V(3.43V) (based on RSEL) through an internal pass transistor capable of delivering 300mA (Typically). The active-state voltage at this pin is regulated through an external NPN or NMOS transistor connected at the DRV2 pin for both 2.5V(2.6V) and 3.3V(3.43V) setting. During all operating states, the voltage at this pin is monitored for under-voltage events.
Description
Operation The RT9641A/B controls 3 output voltages. It is designed for microprocessor computer applications with 3.3V, 5V, 5VSB, and 12V outputs from an ATX power supply. The IC is composed of two linear controllers supplying the PCI slots' 3.3VAUX power (3.3VDUAL, VOUT1) and the 2.5V RDRAM or 3.3V SDRAM memory power (2.5V/3.3V(2.6V/3.43V) VMEM, VOUT2), and a dual switch controller supplying the 5VDUAL voltage (VOUT3). In addition, all the control and monitoring functions necessary for complete ACPI implementation are integrated into the RT9641A/B. Initialization The RT9641A/B automatically initializes upon receipt of input power. The Power-On Reset (POR) function continually monitors the 5VSB input supply voltage, initiating soft-start operation after it exceeds its POR threshold (in S4/S5 states). The 5VSB POR trip event is also used to lock in the memory voltage setting based on RSEL. The RT9641A/B forces the operation mode to start from S4/S5 states at POR releasing. Table 1. 3.3VDUAL Output (VOUT1) Truth Table EN3VDL S5 S3 3V3D 0 0 0 0 1 1 1 1 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 3.3V 3.3V Note 3.3V 3.3V 3.3V Note 0V Comments S0, S1 States (Active) S3 Maintains Previous State S4/S5 S0, S1 States (Active) S3 Maintains Previous State S4/S5 Operational Truth Tables The EN3VDL and EN5VDL pins offer a host of choices in terms of the overall system architecture and supported features. Tables 1~3 describe the truth combinations pertaining to each of the three outputs.
Note: Combination not allowed. As seen in Table 1, EN3VDL simply controls whether the 3.3VDUAL plane remains powered up during S4/S5 sleep state.
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Table 2. 5VDUAL Output (VOUT3) Truth Table EN5VDL S5 S3 5VDL 0 0 0 0 1 1 1 1 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 5V 0V Note 0V 5V 5V Note 5V Comments S0, S1 States(Active) S3 Maintains Previous State S4/S5 S0, S1 States(Active) S3 Maintains Previous State S4/S5 state. Exceeding the maximum current rating of this output in a sleep state can lead to output voltage drooping. If excessive, this droop can ultimately trip the under-voltage detector and send a FAULT signal to the computer system. However, a FAULT condition will only set off the FAULT flag, and it will not shut off or latch off any part of the circuit. If shutdown or latch off the circuit is desired, this can be achieved by externally pulling or latching the SS pin low. Pulling the SS pin low will also force the FAULT pin to go low. Under-voltage sensing is disabled on all disabled outputs and during soft-start ramp-up intervals. Another condition that could set off the FAULT flag is chip over-temperature. If the RT9641A/B reaches an internal temperature of 145C (typical), the FAULT flag is set (FAULT/MSEL pulled high), but the chip Table 3. 2.5V/3.3V(2.6V/3.43V) VMEM Output (VOUT2) Truth Table RSEL S5 S3 1K 1K 1K 1K 10K 10K 10K 10K 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 2.5V/3.3V 2.5V/2.6V 2.5V Note 0V 3.3V/3.43V 3.3V Note 0V Comments S0, S1 States(Active) S3 Maintains Previous State S4/S5 S0, S1 States(Active) S3 Maintains Previous State S4/S5 continues to operate until the temperature reaches 155C (typical), when unconditional shutdown of all outputs takes place. The thermal shutdown can be released with a re-soft-start when the chip cools down. Shutdown In case of a FAULT condition that might endanger the computer system, or at any other time, the RT9641A/B can be shut down by pulling the SS pin below the specified shutdown level (typically 0.8V) with an open drain or open collector device capable of sinking a minimum of 2mA. Pulling the SS pin low effectively shuts down all the pass elements. Upon release of the SS pin, the RT9641A/B undergoes a new soft-start cycle and resumes normal operation in accordance to the ATX supply and control pins status. Layout Considerations The typical application employing a RT9641A/B is a fairly straight-forward implementation. Similar to any other linear regulators, attention has to be paid to a few potentially sensitive small signal components, such as those connected to high-impedance nodes or those supplying critical by-pass currents.
Note: Combination not allowed. Very similarly, Table 2 details the fact that EN5VDL status controls whether the 5VDUAL plane supports sleeps states.
Note: Combination not allowed. As seen in Table 3, 2.5V/3.3V(2.6V/3.43V) VMEM output is maintained in S3 (Suspend-To-RAM), but not in S4/S5 state. The dual-voltage support accommodates both SDRAM as well as RDRAM type memories. Fault Protection All the outputs are monitored against under-voltage events. A serve over-current caused by a failed load on any of the outputs, would, in turn, cause that specific output to suddenly drop. If any of the output voltages drop below 68% of their set value, such event is reported by having the FAULT/MSEL pin pulled to 5V. Additionally, the 2.5V/3.3V(2.6V/3.43V) memory regulator is internally current limited while in a sleep
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RT9641A/B
The power components (pass transistors) and the controller IC should be placed first. The controller should be placed in a central position on the motherboard, closer to the memory load if possible. Ensure the VSEN2 connection is properly sized to carry 300mA without significant resistive losses. The pass transistors should be placed on pads capable of heatsinking, matching the device's power dissipation. Where applicable, multiple via corrections to a large internal plane can significantly lower localized device temperature rise. capacitor placement, but having these capacitors close to the load they serve is preferable. The only critical small signal component is the softstart capacitor, CSS. Locate the component close to SS pin of the control IC and connect to ground though a vias placed close to the capacitor's ground pad. Minimize any leakage current paths from SS node, since the internal current source is only 5A. A multi-layer printed circuit board is recommended. Fig.1 shows the connections represent of most of the components to the converter. Note that each individual capacitor
+12VIN +5VSB C12V C5VSB CI N
could
numerous
physical
capacitors. Dedicate one solid layer for a ground plane and make all critical component ground connections through vias placed as close to the component as possible. Dedicate another solid layer as a power plane and break this plane into smaller islands of common voltage levels. Ideally, the power plane should
Q4 VOUT3 LOAD CHF3 3V3DL RT9641A/B DLA CBULK3 Q5 VOUT2 +5V IN CBULK2 GND DRV2 Q1 CHF2 LOAD
CHF1
CSS Q2 VOUT1
12V SS
5VSB 5VDLSB
support both the input power and output power nodes. Use copper filled polygons on the top and bottom circuit layers to create power islands connecting the filtering components (output capacitors) and the loads. Use the remaining printed circuit layers for small signal wiring.
3V3DLSB 5VDL
LOAD
CBULK1 VSEN2
Q3
Component Selection Guidelines
Output Capacitors Selection The output capacitors for all outputs should be selected to allow the output voltage to meet the dynamic regulation requirements of active state operation (S0, S1). The load transient for the various microprocessor system's components may require high quality capacitors to supply the high slew rate (di/dt) current demands. Thus, it is recommended that capacitors COUT1 and COUT2 should be selected for transient load regulation. Also, during the transition between active and sleep states, there is a short interval of time during which none of the power pass elements are conductingduring this time the output capacitors have to supply all the output current. The output voltage drop during this brief period of time can be approximated with the following formula: VOUT = IOUT x (ESROUT + tt / COUT), where
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+3.3VI N ISLAND ON POWER PLANE LAYER ISLAND ON CIRCUIT/POWER PLANE LAYER VIA CONNECTION TO GROUND PLANE
Fig.1 Printed Circuit Board Islands Placement of the decoupling and bulk capacitors should follow a placement reflecting their purpose. As such, the high-frequency decoupling capacitors (CHF) should be placed as close as possible to the load they are decoupling; the ones decoupling the controller (C12V, C5VSB) close to the controller pins, the one decoupling the load close to the load connector or the load itself (if embedded). The bulk capacitance (aluminum electrolytic or tantalum capacitors) placement is not as critical as the high-frequency
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VOUT : output voltage drop criteria for the selection of this transistor is output voltage budgeting. The maximum RDS(ON) allowed at highest junction temperature can be expressed with the following equation: RDS(ON) MAX = (VIN MIN-VOUT MIN)/ IOUT MAX, where VIN MIN: minimum input voltage VOUT MIN: minimum output voltage allowed. IOUT MAX: maximum output current The gate bias available for this MOEFET is approximately 6V, so the logic level MOSFET is prefered. The 3.3V(3.43V) VMEM power also can be regulated from ATX 5V in order to have high quality VMEM, in such a configuration, either MOSFET or NPN transistors can be used. While the heat dissipation should be carefully handled. Q4 If a P-chanel MOSFET is used to switch the 5VSB output of the ATX supply into the 5VDUAL output during S3 and S4/S5 states (as dictated by EN5VDL status), then, similar to the situation where Q1 is a MOSFET, the selection criteria of this device is also proper voltage budgeting. The maximum rDS (ON), however, has to be achieved with only 4.5V of VGS, so a logic level MOSFET needs to be selected. If a PNP device is chosen to perform this function, it has to have a low saturation voltage while providing the maximum sleepstate current and have current gain sufficiently high to be saturated using the minimum drive current (typically 20mA). A 100~200 resistor is recommended to be inserted between the 5VDLSB pin and Base node of the PNP transistor for limiting the base current. Q3, Q5 The two N-channel MOSFETs are used to switch the 3.3V and 5V inputs provided by the ATX supply into the 3.3VDUAL and 5VDUAL outputs, respectively, while in active (S0, S1) state. Similar RDS(ON) criteria apply in these cases as well, unlike the PMOS, however, these NMOS transistors get the benefit of an increased VGS drive (approximately 8V and 7V respectively). Q2 The NPN transistor used as sleep-state pass element on the 3.3VDUAL output must have a minimum current gain of 100 at VCE = 1.5V and ICE = 500mA throughout the in-circuit operating temperature range.
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ESROUT: output capacitor bank ESR IOUT: output current during transition COUT: output capacitor bank capacitance tt: active-to-sleep or sleep-to-active transition time (5S typical) Since the output voltage drop is heavily dependent on the ESR (equivalent series resistance) of the output capacitor bank, the capacitors should be chosen to maintain the output voltage above the lowest allowable regulation level. Input Capacitors Selection The input capacitors for an RT9641A/B application must have sufficiently low ESR so that the input voltage does not dip excessively when energy is transferred to the output capacitors.
Transistor Selection/Considerations
The RT9641A/B typically requires one P-channel or PNP transistor and two N-channel power MOSFETs and two bipolar NPN transistors. One general requirement for selection of transistors for all the linear regulators/switching elements is package selection for efficient removal of heat. The power dissipated in a linear regulator/switching element is: PLINEAR = IO x (VIN - VOUT) Select a package and heatsink that maintains the junction temperature below the rating maximum expected ambient temperature. Q1 The active element on the 2.5V/3.3V (2.6V/3.43V) VMEM output has different requirements for each the two voltage settings. In 2.5V systems utilizing RDRAM (or voltage-compatible) memory, Q1 had better to be a bipolar NPN capable of conducting the maximum required output current and it must have a minimum current gain (hfe) of 100~150 at this current and 0.7V VCE. In such systems, the 2.5V(2.6V) output is regulated from the ATX 3.3V output while in an active state. In 3.3V systems (SDRAM or compatible) Q1 is suggested to use an N-channel MOSFET, then the MOSFET serves like a switch when it is connected to ATX3.3V during active states (S0, S1). The main
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Typical Application Circuit
+5VIN +12VIN +3.3VIN +5VSB C2 1F + C1 10F C4 1F 12V Q2 2SD1802 Q3 1/2 UF76113DK8 C6 1F + C7 200F R1 1K 3V3DL VSEN2 FAULT/MSEL RT9641A/B 5VDLSB DLA S3 S5 EN5VDL EN3VDL SHUTDOWN (From Open-drain N-MOS) S3 S5 EN5VDL 5VDL EN3VDL SS GND C8,9 + 2X150F 100 R2 Q5 1/2 HUF76113DK8 VOUT3 5VDUAL 3V3DLSB CEB603AL DRV2 VOUT1 3.3VDUAL Q1 2SD1802 VOUT2 3.3V/3.43 VMEM 2X150F C10 1F 1F VOUT2 2.5VMEM Q4 MMBT2907A 5VSB + C3 220F C5 1F ER800D + C14 470F
+
+ C11 150F
C12 1F
C13 0.1F
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Package Information
H M
B
B
J
A C F D
I
Symbol A B C D F H I J M
Dimensions In Millimeters Min 9.804 3.810 1.346 0.330 1.194 0.178 0.102 5.791 0.406 Max 10.008 3.988 1.753 0.508 1.346 0.254 0.254 6.198 1.270
Dimensions In Inches Min 0.386 0.150 0.053 0.013 0.047 0.007 0.004 0.228 0.016 Max 0.394 0.157 0.069 0.020 0.053 0.010 0.010 0.244 0.050
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RICHTEK TECHNOLOGY CORP.
Headquarter
6F, No. 35, Hsintai Road, Chupei City Hsinchu, Taiwan, R.O.C. Tel: (8863)5510047 Fax: (8863)5537749
RICHTEK TECHNOLOGY CORP.
Taipei Office (Marketing)
8F-1, No. 137, Lane 235, Paochiao Road, Hsintien City Taipei County, Taiwan, R.O.C. Tel: (8862)89191466 Fax: (8862)89191465 Email: marketing@richtek-ic.com.tw
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